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ATmega128
Table 41. Overriding Signals for Alternate Functions in PE3..PE0
Signal Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
PE3/AIN1/OC3A
0
0
0
0
OC3B ENABLE
OC3B
0
0
0
AIN1 INPUT
PE2/AIN0/XCK0
0
0
0
0
UMSEL0
XCK0 OUTPUT
0
0
XCK0 INPUT
AIN0 INPUT
PE1/PDO/TXD0
TXEN0
0
TXEN0
1
TXEN0
TXD0
0
0
–
–
PE0/PDI/RXD0
RXEN0
PORTE0 ? PUD
RXEN0
0
0
0
0
0
RXD0
–
Alternate Functions of
Port F
The Port F has an alternate function as analog input for the ADC as shown in Table 42 . If some
Port F pins are configured as outputs, it is essential that these do not switch when a conversion
is in progress. This might corrupt the result of the conversion. In ATmega103 compatibility mode
Port F is input only. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI),
PF5(TMS), and PF4(TCK) will be activated even if a Reset occurs.
Table 42. Port F Pins Alternate Functions
Port Pin
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
Alternate Function
ADC7/TDI (ADC input channel 7 or JTAG Test Data Input)
ADC6/TDO (ADC input channel 6 or JTAG Test Data Output)
ADC5/TMS (ADC input channel 5 or JTAG Test Mode Select)
ADC4/TCK (ADC input channel 4 or JTAG Test ClocK)
ADC3 (ADC input channel 3)
ADC2 (ADC input channel 2)
ADC1 (ADC input channel 1)
ADC0 (ADC input channel 0)
? TDI, ADC7 – Port F, Bit 7
ADC7, Analog to Digital Converter, Channel 7 .
TDI, JTAG Test Data In: Serial input data to be shifted in to the Instruction Register or Data Reg-
ister (scan chains). W hen the JTAG interface is enabled, this pin can not be used as an I/O pin.
? TDO, ADC6 – Port F, Bit 6
ADC6, Analog to Digital Converter, Channel 6 .
TDO, JTAG Test Data Out: Serial output data from Instruction Register or Data Register. W hen
the JTAG interface is enabled, this pin can not be used as an I/O pin.
The TDO pin is tri-stated unless TAP states that shift out data are entered.
? TMS, ADC5 – Port F, Bit 5
ADC5, Analog to Digital Converter, Channel 5 .
82
2467X–AVR–06/11
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